TSMC’s 5nm process to commence trials from April 2019

As the world’s number one foundry, TSMC has a whole lot of work to do if it hopes to remain in that position. We have barely seen chips that use the 7nm process and now, the company has already gotten to advanced stages with the 5nm development. The 7nm EUV lithography process has been completed for the first time, and the 5nm process will begin trial production in April 2019.

However, as we all know, the semiconductor process is a high-precision technology that requires a lot of work. The new process is not completely developed by TSMC. Instead, it relies on the supply of equipment and tech from the industry chain. For example, its lithography machine comes from Dutch ASML. It is understood that in TSMC’s 5nm production line, there will be a 5nm plasma etching machine from Shenzhen Zhongwei Semiconductor, which has been independently developed and has recently passed the verification of TSMC. Micro-Semiconductor and TSMC have cooperated in the 28nm, 10nm and 7nm processes. Now they have successfully moved into the most advanced 5nm process.

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According to reports, plasma etching machine is a key device in chip manufacturing, used for micro-engraving on the chip. The processing precision of each line and the deep hole is a few thousandths to tens of thousands of hair diameter. The precision control requirements are very high. For example, the micro-logic device of the 16nm process has more than 60 layers of microstructures, and it takes more than 1,000 process steps to overcome tens of thousands of technical details.

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For a long time, the core technology of the etching machine has been monopolized by a few manufacturers, micro-semiconductor started from the 65nm plasma dielectric etching machine, 45nm, 32nm, 28nm, 16nm, 10nm all the way down to 7nm. The 5nm etching machine will be adopted by TSMC. However, it is necessary to pay special attention to the fact that micro-semiconductor is able to produce a 5 nm etching machine but there is still a lot of work to be done before a 5nm chip is developed.

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